M64893AFP/AGP

SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR

MITSUBISHI BIPOLAR DIGITAL ICs

MITSUBISHI

-12

Method of setting data

BS4 BS3 BS2 BS1

M8 M7

M6 M5

M4 M3

M2 M1

M0 S4

S3 S2

S1 S0

M9

BAND SW

DATA

READ INTO LATCH

M COUNTER DIVISION

RATIO SETTING

S COUNTER DIVISION

RATIO SETTING

READ INTO LATCH

The frequency demultiplying ratio uses 15bits. Setting up the band switching output uses 4bits.

The test mode data uses 8bits. The total bits used is 27bits.Data is read in when the enable signal is "H" and

the clock signal falls.

The band switching data is read in at the 4th pulse of the clock signal.The program counter data is read into

the latch by the fall of the 19th pulse of the clock signal. When the enable signal goes to "L" before the 19th

pulse of the enable signal, only the band SW data is updated and other data is ignored.

The data is latched at the 19th pulse of the clock signal. At this time, 1/640 frequency division ratio is

used. Clock signals after the above are invalid.

How to set the dividing ratio of the programmable divider

Total division N is given by the following formulas in addition to the prescaler used in the previous stage.

N=8 • (32M + S)

M : 10 bit main counter division

S : 5 bit swallow counter division

The M and S counters are binary the possible ranges of division are as follows.

32

≤ M ≤ 1023

O

≤ S ≤ 31

Therefore,the range of division N is 8,192 to 262,136.

=6.25 x 8 x (32M + S)

=50.0 x (32M + S)

[ kHz ]

But,the tuning frequency range is 51.2MHz to 1300Mz from the maximum prescaler operating

frequency.

3

E N A

D A T A

C L K