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5/21/01; v.1.1

Alliance Semiconductor

P. 20 of 29

AS4LC2M8S1

AS4LC1M16S1

read interrupted by write (CL = 2, BL = 4)

To prevent bus contention, maintain a gap between data in and data out.

read interrupted by write (CL = 3, BL = 4)

To prevent bus contention, maintain a gap between data in and data out.

Burst termination

Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read

cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle,

burst write data is terminated and the databus goes to High Z simultaneously.

CLK

CMD1

DQM1

DQ1

CMD2

DQM2

DQ2

CMD3

DQM3

DQ3

CMD4

DQM4

DQ4

Write data

Read data

Write data

Read data

Write data

Read data

Write data

Read data

CLK

CMD1

DQ1

CMD2

DQM2

DQ2

CMD3

DQM3

DQ3

CMD4

DQM4

DQ4

Read data

Write data

Read data

Write data

Read data

Write data

Read data

Write data

DQM1