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71M6545HT-IGT/F bảng dữ liệu(PDF) 47 Page - Maxim Integrated Products

tên linh kiện 71M6545HT-IGT/F
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71M6545HT-IGT/F bảng dữ liệu(HTML) 47 Page - Maxim Integrated Products

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71M6545T/71M6545HT
Energy Meter ICs
www.maximintegrated.com
Table 12. I/O RAM Locations in Numerical Order (continued)
Table 13. I/O RAM Locations in Alphabetical Order
NAME
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RTC13
289E
U
U
RTC_TMIN[5:0]
RTC14
289F
U
U
U
RTC_THR[4:0]
TEMP
28A0
TEMP_BSEL
TEMP_PWR
OSC_COMP
TEMP_BAT
TBYTE_BUSY
TEMP_PER[2:0]
WF1
28B0
WF_CSTART
WF_RST
WF_RSTBIT
WF_OVF
WF_ERST
WF_BADVDD
U
U
WF2
28B1
U
WF_TEMP
WF_TMR
WF_RX
WF_PB
WF_DIO4
U
WF_DIO55
MISC
28B2
SLEEP
U
WAKE_ARM
U
U
U
U
U
WAKE_E
28B3
U
EW_TEMP
U
EW_RX
EW_PB
EW_DIO4
U
EW_DIO55
WDRST
28B4
WD_RST
TEMP_START
U
U
U
U
U
U
MPU PORTS
P3
SFR B0
DIO_DIR[15:12]
DIO[15:12]
P2
SFR A0
DIO_DIR[11:8]
DIO[11:8]
P1
SFR 90
DIO_DIR[7:4]
DIO[7:4]
P0
SFR 80
DIO_DIR[3:0]
DIO[3:0]
FLASH
FLSH_ERASE SFR 94
FLSH_ERASE[7:0]
FLSH_CTL SFR B2
PREBOOT
SECURE
U
U
FLSH_PEND
FLSH_PSTWR
FLSH_MEEN
FLSH_PWE
FLSH_
PGADR
SFR B7
FLSH_PGADR[6:0]
U
I2C
EEDATA
SFR 9E
EEDATA[7:0]
EECTRL
SFR 9F
EECTRL[7:0]
NAME
LOCATION RST WK DIR
DESCRIPTION
ADC_E
2704[4]
0
0 R/W Enables ADC and VREF. When disabled, reduces bias current.
ADC_DIV
2200[5]
0
0 R/W
ADC_DIV controls the rate of the ADC and FIR clocks.
The ADC_DIV setting determines whether MCK is divided by 4 or 8:
0 = MCK/4
1 = MCK/8
The resulting ADC and FIR clock is as shown below.
PLL_FAST = 0
PLL_FAST = 1
MCK
6.291456MHz
19.660800MHz
ADC_DIV = 0
1.572864MHz
4.9152MHz
ADC_DIV = 1
0.786432MHz
2.4576MHz
BCURR
2704[3]
0
0 R/W Connects a 100µA load to the battery selected by TEMP_BSEL.
BSENSE[7:0]
2885[7:0]
–
–
R The result of the battery measurement.
CE_E
2106[0]
0
0 R/W CE enable.
CE_LCTN[5:0]
2109[5:0]
31 31 R/W CE program location. The starting address for the CE program is 1024 x CE_LCTN.
CHIP_ID[15:0]
2300[7:0]
2301[7:0]
0
0
0
0
R
R
Thesebytescontainthechipidentification.
CHIP_ID[15:0]:
71M6545T (11B4h)
71M6545HT (11BCh)



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