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AM2432BSDFHIALVR bảng dữ liệu(HTML) 88 Page - Texas Instruments |
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88 / 242 page  Table 6-65. PRU_ICSSG1 Signal Descriptions (continued) Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] PRG1_PWM2_B2 IO PRU_ICSSG1 PWM Output B R16, W12 V20, Y12 PRG1_PWM3_A0 IO PRU_ICSSG1 PWM Output A Y7 V4 PRG1_PWM3_A1 IO PRU_ICSSG1 PWM Output A AA7 Y2 PRG1_PWM3_A2 IO PRU_ICSSG1 PWM Output A V8 Y5 PRG1_PWM3_B0 IO PRU_ICSSG1 PWM Output B U8 W5 PRG1_PWM3_B1 IO PRU_ICSSG1 PWM Output B U13 V13 PRG1_PWM3_B2 IO PRU_ICSSG1 PWM Output B V13 U14 PRG1_RGMII1_RXC I PRU_ICSSG1 RGMII Receive Clock AA7 Y2 PRG1_RGMII1_RX_CTL I PRU_ICSSG1 RGMII Receive Control Y8 AA5 PRG1_RGMII1_TXC IO PRU_ICSSG1 RGMII Transmit Clock V9 W6 PRG1_RGMII1_TX_CTL O PRU_ICSSG1 RGMII Transmit Control Y9 Y7 PRG1_RGMII2_RXC I PRU_ICSSG1 RGMII Receive Clock U11 V10 PRG1_RGMII2_RX_CTL I PRU_ICSSG1 RGMII Receive Control W12 Y12 PRG1_RGMII2_TXC IO PRU_ICSSG1 RGMII Transmit Clock Y10 Y8 PRG1_RGMII2_TX_CTL O PRU_ICSSG1 RGMII Transmit Control Y11 V9 PRG1_RGMII1_RD0 I PRU_ICSSG1 RGMII Receive Data Y7 V4 PRG1_RGMII1_RD1 I PRU_ICSSG1 RGMII Receive Data U8 W5 PRG1_RGMII1_RD2 I PRU_ICSSG1 RGMII Receive Data W8 AA4 PRG1_RGMII1_RD3 I PRU_ICSSG1 RGMII Receive Data V8 Y5 PRG1_RGMII1_TD0 O PRU_ICSSG1 RGMII Transmit Data AA8 V5 PRG1_RGMII1_TD1 O PRU_ICSSG1 RGMII Transmit Data U9 W2 PRG1_RGMII1_TD2 O PRU_ICSSG1 RGMII Transmit Data W9 V6 PRG1_RGMII1_TD3 O PRU_ICSSG1 RGMII Transmit Data AA9 AA7 PRG1_RGMII2_RD0 I PRU_ICSSG1 RGMII Receive Data W11 AA10 PRG1_RGMII2_RD1 I PRU_ICSSG1 RGMII Receive Data V11 Y10 PRG1_RGMII2_RD2 I PRU_ICSSG1 RGMII Receive Data AA12 Y11 PRG1_RGMII2_RD3 I PRU_ICSSG1 RGMII Receive Data Y12 V12 PRG1_RGMII2_TD0 O PRU_ICSSG1 RGMII Transmit Data AA10 Y6 PRG1_RGMII2_TD1 O PRU_ICSSG1 RGMII Transmit Data V10 AA8 PRG1_RGMII2_TD2 O PRU_ICSSG1 RGMII Transmit Data U10 Y9 PRG1_RGMII2_TD3 O PRU_ICSSG1 RGMII Transmit Data AA11 W9 PRG1_UART0_CTSn I PRU_ICSSG1 UART Clear to Send (active low) U15 W16 PRG1_UART0_RTSn O PRU_ICSSG1 UART Request to Send (active low) U14 W13 PRG1_UART0_RXD I PRU_ICSSG1 UART Receive Data V14 Y16 PRG1_UART0_TXD O PRU_ICSSG1 UART Transmit Data W14 U13 (1) The PRG1_IEP0_EDIO_OUTVALID signal is not supported by the AM243x_ALX device package. See AM243x_ALX Package - Unsupported Interfaces and Signals for additional details. 6.3.21 Reserved Table 6-66. Reserved Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] RSVD0 (1) RSVD Reserved (RSVD0) H16 H11 RSVD1 (1) RSVD Reserved (RSVD1) D21 J13 RSVD2 (1) RSVD Reserved (RSVD2) G13 RSVD3 (1) RSVD Reserved (RSVD3) F17 RSVD4 (1) RSVD Reserved (RSVD4) W15 RSVD5 (1) RSVD Reserved (RSVD5) V16 RSVD6 (1) RSVD Reserved (RSVD6) K2 RSVD7 (1) RSVD Reserved (RSVD7) K1 AM2434, AM2432, AM2431 SPRSP65C – APRIL 2021 – REVISED MARCH 2022 www.ti.com 88 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM2434 AM2432 AM2431 |
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