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AM2432BSDFHIALVR bảng dữ liệu(HTML) 81 Page - Texas Instruments |
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81 / 242 page  Table 6-63. Power Supply Signal Descriptions (continued) Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] VDDA_3P3_SDIO PWR SDIO 3.3 V analog supply H15 K15 VDDA_3P3_USB0 PWR USB0 3.3 V analog supply R13 U16 VDDA_ADC PWR ADC0 analog supply J13 G17, H17 VDDA_MCU PWR POR and MCU PLL analog supply K12 H14 VDDA_PLL0 PWR MAIN, PER1, and R5F PLL analog supply N12 N12 VDDA_PLL1 PWR ARM and DDR PLL analog supply H9 G9 VDDA_PLL2 PWR PER0 PLL analog supply J11 G12 VDDA_TEMP0 PWR TEMP0 analog supply G11 G11 VDDA_TEMP1 A TEMP1 analog supply L11 M11 VDDR_CORE PWR RAM supply L10 G5, G6, J10, J12, P14, P8, R10 VDDSHV0 PWR IO supply for IO group 0 F11 C13, D13, E14 VDDSHV1 PWR IO supply for IO group 1 M7 L6, M6, P5, P6 VDDSHV2 PWR IO supply for IO group 2 R8 T11, T8, U11, U7, U8 VDDSHV3 PWR IO supply for IO group 3 P14 R17, T17 VDDSHV4 PWR IO supply for IO group 4 M14 N16, N17 VDDSHV5 PWR IO supply for IO group 5 L14 L16, L17 VDDSHV_MCU PWR IO supply for IO MCU F9 E7, E8, E9 VDDS_DDR PWR DDR PHY IO supply F7 VDDS_DDR_C PWR DDR clock IO supply J8 VDDS_MMC0 PWR MMC0 PHY IO supply J15 VDDS_OSC PWR MCU_OSC0 supply H13 F18 VDD_CORE PWR Core supply J10 F11, G10, H15, H8, J9, K11, K14, L13, L9, M14, M8, N10, N9, R12, R13, R9 VDD_DLL_MMC0 PWR MMC0 PLL analog supply H14 VDD_MMC0 PWR MMC0 PHY core supply K13 VPP PWR eFuse ROM programming supply G15 E16 VSS GND Ground A1, A21, AA1, AA15, AA18, AA21, C10, C15, C3, D1, E11, E13, F10, F15, F8, G1, G16, G3, G7, G9, H11, H20, H21, H6, H8, J14, J16, J7, J9, K6, K8, L1, L16, L3, L7, L9, M10, M12, M6, M8, N11, N13, N15, N7, N9, P1, P10, P18, P6, P8, R12, R7, R9, T10, T11, T15, T16, T8, U3, V17, W10, W18, Y14, Y17, Y19 A1, A2, A20, A21, AA1, AA2, AA20, AA21, B1, B21, D10, D16, D17, E11, E13, E6, F17, F8, G16, H16, H6, H7, J11, J16, J5, J6, K16, K6, K7, K8, L10, L11, L12, M15, M16, M7, N11, N13, N6, P11, P15, P16, P7, R11, R6, T14, U6, Y1, Y21 (1) This pin must always be connected via a 1-μF capacitor to VSS. (2) The CAP_VDDSHV_MMC1 pin must always be connected via a 3.3-μF ±20% capacitor to VSS. 6.3.20 PRU_ICSSG MAIN Domain Instances Table 6-64. PRU_ICSSG0 Signal Descriptions Signal Name [1] Signal Type [2] Description [3] ALV PIN [4] ALX PIN [4] PRG0_ECAP0_IN_APWM_OUT IO PRU_ICSSG0 Enhanced Capture (ECAP) Input or Auxiliary PWM (APWM) Ouput R2, U5 F3, M4 PRG0_ECAP0_SYNC_IN I PRU_ICSSG0 ECAP Sync Input P5, V5 D1, T1 www.ti.com AM2434, AM2432, AM2431 SPRSP65C – APRIL 2021 – REVISED MARCH 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: AM2434 AM2432 AM2431 |
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