STM32F107RC datasheet(38/108 Pages) STMICROELECTRONICS

38 / 108 page

Electrical characteristics

STM32F105xx, STM32F107xx

38/108

DocID15274 Rev 10

5.3.2

Operating conditions at power-up / power-down

Subject to general operating conditions for TA.

5.3.3

Embedded reset and power control block characteristics

The parameters given in Table 11 are derived from tests performed under ambient

temperature and VDD supply voltage conditions summarized in Table 9.

Table 10. Operating condition at power-up / power down

Symbol

Parameter

Condition

Min

Max

Unit

tVDD

VDD rise time rate

µs/V

VDD fall time rate

Table 11. Embedded reset and power control block characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VPVD

Programmable voltage

detector level selection

PLS[2:0]=000 (rising edge)

2.1

2.18

2.26

PLS[2:0]=000 (falling edge)

2.08

2.16

PLS[2:0]=001 (rising edge)

2.19

2.28

2.37

PLS[2:0]=001 (falling edge)

2.09

2.18

2.27

PLS[2:0]=010 (rising edge)

2.28

2.38

2.48

PLS[2:0]=010 (falling edge)

2.18

2.28

2.38

PLS[2:0]=011 (rising edge)

2.38

2.48

2.58

PLS[2:0]=011 (falling edge)

2.28

2.38

2.48

PLS[2:0]=100 (rising edge)

2.47

2.58

2.69

PLS[2:0]=100 (falling edge)

2.37

2.48

2.59

PLS[2:0]=101 (rising edge)

2.57

2.68

2.79

PLS[2:0]=101 (falling edge)

2.47

2.58

2.69

PLS[2:0]=110 (rising edge)

2.66

2.78

2.9

PLS[2:0]=110 (falling edge)

2.56

2.68

2.8

PLS[2:0]=111 (rising edge)

2.76

2.88

PLS[2:0]=111 (falling edge)

2.66

2.78

2.9

VPVDhyst(2)

PVD hysteresis

100

VPOR/PDR

Power on/power down

reset threshold

Falling edge

1.8(1)

1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.

1.88

1.96

Rising edge

1.84

1.92

2.0

VPDRhyst(2)

PDR hysteresis

TRSTTEMPO(2)

2. Guaranteed by design, not tested in production.

Reset temporization

2.5

4.5

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