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STM32WB15CC bảng dữ liệu(PDF) 36 Page - STMicroelectronics

tên linh kiện STM32WB15CC
Giải thích chi tiết về linh kiện  Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution
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STM32WB15CC bảng dữ liệu(HTML) 36 Page - STMicroelectronics

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Functional overview
STM32WB15CC
36/127
DS13258 Rev 4
Figure 7. Clock tree
3.11
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked, if needed, following a specific
sequence in order to avoid spurious writing to the I/Os registers.
MS53136V4
SMPS clock
source control
LSI1 RC 32 kHz
LSI2 RC 32 kHz
LSE OSC
32.768 kHz
LSCO
LSI
to IWDG
HSE OSC
32 MHz
HSE CSS
OSC_IN
OSC_OUT
HSI16 RC
16 MHz
MSI RC
100 kHz - 48 MHz
MCO
/1 - 16
/32
LSE CSS
/32
PLL
/P
/R
/Q
/M
SYSCLK
MSI
MSI
HSI
HSI16
HSE
PRE
HSE
PLLRCLK
PLLRCLK
LSE
LSI2
LSI1
SYS clock
source control
SYSCLK
MSI
HSI16
HSEPRE
HCLK1
HCLK2
HCLK4
APB1
PPRE1
/1,2,4,8,16
to CPU1, AHB1, AHB2 and SRAM1
to CPU1 FCLK
/8
to CPU1 system timer
APB2
PPRE2
/1,2,4,8,16
PCLK1
PCLK2
to CPU2
to CPU2 FCLK
/8
to CPU2 system timer
to AHB4, Flash memory and SRAM2
to APB1 TIMx
to APB2 TIMx
to USART1
to LPTIMx
to LPUART1
to ADC
to RTC
x1 or
x2
x1 or
x2
to I2C1
PCLKn
SYSCLK
HSI16
HSI16
PCLKn
LSI
LSE
PLLPCLK
SYSCLK
PCLKn
LSE
to BLE wakeup
/2
HCLK5
HSI
HSE
to AHB5
to APB3
to APB2
to APB1
to RF
SYSCLK
MSI
PLLQCLK
PLLRCLK
OSC32_IN
OSC32_OUT
LSI
LSE
LSE
MSI
HSI
HSE
SMPSDIV
/1,2,3,4,6,8,12
to SMPS
/2
CPU1
HPRE
/1,2,...,512
AHBS
SHDHPRE
/1,2,...,512
CPU2
C2HPRE
1,2,...,512
HSI16
/3
to RNG
LSI
LSE
HSE PRE
/1,2
SMPSDIV
/1,2,4
HSI_V33
HSI
PLLPCLK
xN
LSI



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