STM32WB15CC datasheet(45/127 Pages) STMICROELECTRONICS

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DS13258 Rev 4

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STM32WB15CC

Functional overview

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode using baudrates up to 220 kbaud. The wake up events from Stop

mode are programmable and can be:



the start bit detection



any received data frame



a specific programmed data frame.

Only a 32.768 kHz clock (LSE) is needed for LPUART communication up to 9600 baud.

Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an

extremely low energy consumption. Higher speed clock can be used to reach higher

baudrates.

The LPUART interfaces can be served by the DMA controller.

3.23

Serial peripheral interface (SPI1)

The SPI interface enables communication up to 32 Mbit/s in master and up to 24 Mbit/s in

slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8

master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI

interface support NSS pulse mode, TI mode and Hardware CRC calculation.

The SPI interface can be served by the DMA controller.

3.24

Development support

3.24.1

Serial wire JTAG debug port (SWJ-DP)

The Arm® SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug

port that enables either a serial wire debug or a JTAG probe to be connected to the target.

Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins

can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are

shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is

used to switch between JTAG-DP and SW-DP.

STM32WB15CC bảng dữ liệu(PDF) 45 Page - STMicroelectronics