STM32WB15CC datasheet(17/127 Pages) STMICROELECTRONICS

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DS13258 Rev 4

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STM32WB15CC

Functional overview

SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the

SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the

host CPU1.

The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock

speeds.

3.4

Security and safety

The STM32WB15CC contains many security blocks both for the BLE and the Host

application.

It includes:



Secure Flash memory partition for RF subsystem-only access



Secure SRAM partition, that can be accessed only by the RF subsystem



True random number generator (RNG)



Advance encryption standard hardware accelerator (AES-256bit, supporting chaining

modes ECB, CBC, CTR, GCM, GMAC, CCM)



Private key acceleration (PKA) including:

–

Modular arithmetic including exponentiation with maximum modulo size of 3136

bits

–

Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA

verification with maximum modulo size of 521 bits



Cyclic redundancy check calculation unit (CRC)

A specific mechanism is in place to ensure that all the code executed by the RF subsystem

CPU2 can be secure, whatever the Host application.

3.5

Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:



Boot from user Flash



Boot from system memory



Boot from embedded SRAM

The device always boots on CPU1 core. The embedded bootloader code makes it possible

to boot from various peripherals:



UART



I2C



SPI

Secure Firmware update from system boot is provided.

3.6

RF subsystem

The STM32WB15CC embed an ultra-low power multi-standard radio Bluetooth® Low

Energy (BLE), compliant with Bluetooth® specification 5.2. The BLE features 1 Mbps and

2 Mbps transfer rates, supports multiple roles simultaneously acting at the same time as

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