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STM32WB15CC bảng dữ liệu(PDF) 102 Page - STMicroelectronics

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STM32WB15CC bảng dữ liệu(HTML) 102 Page - STMicroelectronics

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Electrical characteristics
STM32WB15CC
102/127
DS13258 Rev 4
Figure 21. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 67, otherwise the reset is not taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.
Table 67. NRST pin characteristics(1)
1.
Specified by design, not tested in production.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)
NRST input
low level voltage
-
-
-
0.3 x VDD
V
VIH(NRST)
NRST input
high level voltage
-
0.7 x VDD
--
Vhys(NRST)
NRST Schmitt trigger
voltage hysteresis
--
200
-
mV
RPU
Weak pull-up
equivalent resistor(2)
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10%)
.
VIN = VSS
25
40
55
kΩ
VF(NRST)
NRST input
filtered pulse
--
-
70
ns
VNF(NRST)
NRST input
not filtered pulse
1.71 V ≤ VDD ≤ 3.6 V
350
-
-
MS19878V3
RPU
VDD
Internal reset
External
reset circuit
(1)
NRST
(2)
Filter
0.1 μF



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