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STM8AF6213 bảng dữ liệu(PDF) 11 Page - STMicroelectronics |
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STM8AF6213 bảng dữ liệu(HTML) 11 Page - STMicroelectronics |
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11 / 112 page ![]() DS9884 Rev 9 11/112 STM8AF6213/13A/23/23A/26 Block diagram 108 3 Block diagram Figure 1. STM8AF6213/13A/23/23A/26 block diagram 1. Legend: ADC (Analog-to-digital converter), beCAN (Controller area network), BOR (Brownout reset), I²C (Inter-integrated circuit multimaster interface),IWDG (Independent window watchdog), LINUART (Local interconnect network universal asynchronous receiver transmitter), POR (Power on reset), SPI (Serial peripheral interface), SWIM (Single wire interface module), USART (Universal synchronous asynchronous receiver transmitter), Window WDG (Window watchdog). XTAL 1- 16 MHz RC int. 16 MHz RC int. 128 kHz STM8 core Debug/SWIM SPI 8-bit basic timer (TIM6) Reset block Reset POR BOR Clock controller Detector Clock to peripherals and core 8 Mbit/s Window WDG Up to 8 Kbyte program Flash 640 byte 1 Kbyte RAM ADC1 Reset 400 Kbit/s Single wire debug interface 16-bit advanced control timer (TIM1) 16-bit general purpose timers (TIM5) data EEPROM Independent WDG 3 CAPCOM channels Up to Up to 7 channels I2C AWU timer LINUART LIN SPI emul. MS38343V1 1/2/4 kHz beep Beeper Up to 4 CAPCOM channels + 3 complementary outputs |
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