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STM32WB35CC bảng dữ liệu(PDF) 116 Page - STMicroelectronics |
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STM32WB35CC bảng dữ liệu(HTML) 116 Page - STMicroelectronics |
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116 / 193 page ![]() Electrical characteristics STM32WB55xx STM32WB35xx 116/193 DS11929 Rev 11 APB1 RTCA 1.10 0.88 1.25 µA/MHz CRS 0.24 0.20 0.20 USB FS independent clock domain 3.20 N/A N/A USB FS clock domain 2.05 N/A N/A I2C1 independent clock domain 2.50 4.40 4.40 I2C1 clock domain 4.80 4.00 5.50 I2C3 independent clock domain 2.10 3.50 3.55 I2C3 clock domain 3.70 3.10 3.55 LCD 1.35 1.10 2.10 SPI2 1.65 1.40 2.25 LPTIM1 independent clock domain 2.10 3.40 3.00 LPTIM1 clock domain 3.60 3.00 3.80 TIM2 5.65 4.70 4.90 LPUART1 independent clock domain 2.70 4.15 3.85 LPUART1 clock domain 4.45 3.70 5.25 LPTIM2 clock domain 3.95 3.25 4.50 LPTIM2 independent clock domain 2.20 3.70 3.80 WWDG 0.335 0.285 0.965 All APB1 peripherals 27.0 22.5 25.5 APB2 AHB to APB2(3) 1.10 0.885 1.35 TIM1 8.20 6.80 7.25 TIM17 2.85 2.40 2.40 TIM16 2.75 2.30 2.55 USART1 independent clock domain 4.40 7.80 7.00 USART1 clock domain 8.80 7.30 7.75 SPI1 1.75 1.45 1.45 SAI1 independent clock domain 2.50 1.50 3.50 SAI1 clock domain 2.40 N/A N/A All APB2 on 28.0 23.0 25.5 ALL 97.5 80.5 90.0 1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA). 2. GPIOs consumption during read and write accesses. 3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2. Table 50. Peripheral current consumption (continued) Peripheral Range 1 Range 2 Low-power run and sleep Unit |
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