PCE85176AUGSLASHDA datasheet(11/48 Pages) NXP

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PCE85176AUG

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Product data sheet

Rev. 1 — 12 January 2015

11 of 48

NXP Semiconductors

PCE85176AUG

4 × 40 LCD segment driver for Chip-On-Glass

7.3.1 Writing to RAM

The addressing mechanism for the display RAM is realized using the data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes, into

any location of the display RAM.

The sequence always commences with the initialize-RAM command (see Table 12).

Following this command, the data pointer has to be set to the desired RAM address using

the load-data-pointer command (see Table 10). After this an arriving data byte is stored at

the display RAM address indicated by the data pointer. The RAM writing procedure is

illustrated in Figure 5 and the filling order of the RAM is shown in Figure 4.

After each byte is stored, the content of the data pointer is automatically incremented by a

value dependent on the selected LCD drive mode:

• In static drive mode by eight.

• In 1:2 multiplex drive mode by four.

• In 1:3 multiplex drive mode by three.

• In 1:4 multiplex drive mode by two.

If an I2C-bus data access terminates early, then the state of the data pointer is unknown.

So, the data pointer must be rewritten before further RAM accesses.

Fig 5.

RAM writing procedure

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