WM8580GEFT datasheet(21/92 Pages) WOLFSON

21 / 92 page

Product Preview

WM8580

PP Rev 1.0 March 2006

SOFTWARE REGISTER RESET

Writing to register R53 will cause a register reset, resetting all register bits to their default values.

Note that the WM8580 is powered down by default so writing to this register will power down the

device.

Table 11 Software Reset

DIGITAL AUDIO INTERFACES

Audio data is transferred to and from the WM8580 via the digital audio interfaces. There are two

receive audio interfaces and two transmit audio interfaces. The digital routing options for these

interfaces are described on page 21. Control of the audio interfaces is described below.

MASTER AND SLAVE MODES

The audio interfaces require both a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be

supplied externally (slave mode) or they can be generated internally (master mode). When in master

mode, the BCLKs and LRCLKs for an interface are output on the corresponding BCLK and LRCLK

pins. By default, all interfaces operate in slave mode, but can operate in master mode by setting the

PAIFTXMS, PAIFRXMS and SAIFMS register bits. In Hardware Control Mode, the PAIF Transmitter

can operate in master mode by setting the SDI pin.

Figure 12 Slave Mode

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R53

RESET

35h

8:0

RESET

n/a

Writing any data value to this register

will apply a reset to the device

registers.

WM8580GEFT bảng dữ liệu(PDF) 21 Page - Wolfson Microelectronics plc