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STM32H750VB bảng dữ liệu(PDF) 179 Page - STMicroelectronics

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STM32H750VB bảng dữ liệu(HTML) 179 Page - STMicroelectronics

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DS12556 Rev 5
179/334
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
Electrical characteristics (rev Y)
311
6.3.29
Camera interface (DCMI) timing specifications
Unless otherwise specified, the parameters given in Table 99 for DCMI are derived from
tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply
voltage summarized in Table 22: General operating conditions, with the following
configuration:
DCMI_PIXCLK polarity: falling
DCMI_VSYNC and DCMI_HSYNC polarity: high
Data formats: 14 bits
Capacitive load C=30 pF
Measurement points are done at CMOS levels: 0.5VDD
Figure 42. DCMI timing diagram
Table 99. DCMI characteristics(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
-
Frequency ratio DCMI_PIXCLK/frcc_c_ck
-0.4
-
DCMI_PIXCLK Pixel clock input
-
80
MHz
DPixel
Pixel clock input duty cycle
30
70
%
tsu(DATA)
Data input setup time
1
-
ns
th(DATA)
Data input hold time
1
-
tsu(HSYNC)
tsu(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input setup time
1.5
-
th(HSYNC)
th(VSYNC)
DCMI_HSYNC/DCMI_VSYNC input hold time
1
-
MS32414V2
DCMI_PIXCLK
tsu(VSYNC)
tsu(HSYNC)
DCMI_HSYNC
DCMI_VSYNC
DATA[0:13]
1/DCMI_PIXCLK
th(HSYNC)
th(HSYNC)
tsu(DATA) th(DATA)



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