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STM32H750VB bảng dữ liệu(PDF) 176 Page - STMicroelectronics

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STM32H750VB bảng dữ liệu(HTML) 176 Page - STMicroelectronics

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Electrical characteristics (rev Y)
STM32H750VB STM32H750ZB STM32H750IB STM32H750XB
176/334
DS12556 Rev 5
6.3.28
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 98 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
summarized in Table 22: General operating conditions, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (DFSDMx_CKINx, DFSDMx_DATINx, DFSDMx_CKOUT for
DFSDMx).
Table 98. DFSDM measured timing - 1.62-3.6 V(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK
DFSDM clock
1.62 V < VDD < 3.6 V
-
-
250
MHz
fCKIN
(1/TCKIN)
Input clock
frequency
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
1.62 V < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
External clock mode
(SPICKSEL[1:0]=0),
2.7 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]
0),
1.62 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
SPI mode (SITP[1:0]=0,1),
Internal clock mode
(SPICKSEL[1:0]
0),
2.7 < VDD < 3.6 V
--
20
(fDFSDMCLK/4)
fCKOUT
Output clock
frequency
1.62 < VDD < 3.6 V
-
-
20
DuCyCKOUT
Output clock
frequency duty
cycle
1.62 < VDD < 3.6 V
45
50
55
%



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