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STM32H750VB bảng dữ liệu(PDF) 135 Page - STMicroelectronics |
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STM32H750VB bảng dữ liệu(HTML) 135 Page - STMicroelectronics |
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135 / 335 page ![]() DS12556 Rev 5 135/334 STM32H750VB STM32H750ZB STM32H750IB STM32H750XB Electrical characteristics (rev Y) 311 Output buffer timing characteristics (HSLV option enabled) Table 62. Output timing characteristics (HSLV ON)(1) Speed Symbol Parameter conditions Min Max Unit 00 Fmax(2) Maximum frequency C=50 pF, 1.62 V≤VDD≤2.7 V - 10 MHz C=30 pF, 1.62 V≤VDD≤2.7 V - 10 C=10 pF, 1.62 V≤VDD≤2.7 V - 10 tr/tf(3) Output high to low level fall time and output low to high level rise time C=50 pF, 1.62 V≤VDD≤2.7 V - 11 ns C=30 pF, 1.62 V≤VDD≤2.7 V - 9 C=10 pF, 1.62 V≤VDD≤2.7 V - 6.6 01 Fmax(3) Maximum frequency C=50 pF, 1.62 V≤VDD≤2.7 V - 50 MHz C=30 pF, 1.62 V≤VDD≤2.7 V - 58 C=10 pF, 1.62 V≤VDD≤2.7 V - 66 tr/tf(4) Output high to low level fall time and output low to high level rise time C=50 pF, 1.62 V≤VDD≤2.7 V - 6.6 ns C=30 pF, 1.62 V≤VDD≤2.7 V - 4.8 C=10 pF, 1.62 V≤VDD≤2.7 V - 3 10 Fmax(3) Maximum frequency C=50 pF, 1.62 V≤VDD≤2.7 V(4) -55 MHz C=30 pF, 1.62 V≤VDD≤2.7 V(5) -80 C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 133 tr/tf(4) Output high to low level fall time and output low to high level rise time C=50 pF, 1.62 V≤VDD≤2.7 V(5) -5.8 ns C=30 pF, 1.62 V≤VDD≤2.7 V(5) -4 C=10 pF, 1.62 V≤VDD≤2.7 V(5) -2.4 11 Fmax(3) Maximum frequency C=50 pF, 1.62 V≤VDD≤2.7 V(5) -60 MHz C=30 pF, 1.62 V≤VDD≤2.7 V(5) -90 C=10 pF, 1.62 V≤VDD≤2.7 V(5) - 175 tr/tf(4) Output high to low level fall time and output low to high level rise time C=50 pF, 1.62 V≤VDD≤2.7 V(5) -5.3 ns C=30 pF, 1.62 V≤VDD≤2.7 V(5) -3.6 C=10 pF, 1.62 V≤VDD≤2.7 V(5) -1.9 1. Guaranteed by design. 2. The maximum frequency is defined with the following conditions: (tr+tf) ≤ 2/3 T Skew ≤ 1/20 T 45%<Duty cycle<55% 3. The fall and rise times are defined between 90% and 10% and between 10% and 90% of the output waveform, respectively. 4. Compensation system enabled. |
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