MCF5373CAB180 datasheet(34/46 Pages) NXP

tên linh kiện	MCF5373CAB180

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MCF537x ColdFire® Microprocessor Data Sheet, Rev. 4

Electrical Characteristics

Freescale Semiconductor

Figure 22. QSPI Timing

5.16

JTAG and Boundary Scan Timing

Table 24. JTAG and Boundary Scan Timing

Num

Characteristics1

1 JTAG_EN is expected to be a static signal. Hence, specific timing is not associated with it.

Symbol

Min

Max

Unit

TCLK Frequency of Operation

fJCYC

1/4

fsys/3

TCLK Cycle Period

tJCYC

4—

tCYC

TCLK Clock Pulse Width

tJCW

—

TCLK Rise and Fall Times

tJCRF

Boundary Scan Input Data Setup Time to TCLK Rise

tBSDST

4—

Boundary Scan Input Data Hold Time after TCLK Rise

tBSDHT

—

TCLK Low to Boundary Scan Output Data Valid

tBSDV

033

TCLK Low to Boundary Scan Output High Z

tBSDZ

033

TMS, TDI Input Data Setup Time to TCLK Rise

tTAPBST

4—

J10

TMS, TDI Input Data Hold Time after TCLK Rise

tTAPBHT

—

J11

TCLK Low to TDO Data Valid

tTDODV

026

J12

TCLK Low to TDO High Z

tTDODZ

J13

TRST Assert Time

tTRSTAT

100

—

J14

TRST Setup Time (Negation) to TCLK High

tTRSTST

—

QSPI_CS[3:0]

QSPI_CLK

QSPI_DOUT

QS5

QS1

QSPI_DIN

QS3

QS4

QS2

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