DLPA2000 datasheet(53/63 Pages) TI

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10.1.5 DMD Control and Sub-LVDS Signals

Table 10-4. Maximum Pin-to-Pin PCB Interconnect Recommendations

DMD BUS SIGNAL(1) (2)

SIGNAL INTERCONNECT TOPOLOGY

UNIT

SINGLE-BOARD SIGNAL

ROUTING LENGTH

MULTI-BOARD SIGNAL

ROUTING LENGTH

DMD_HS_CLK_P

DMD_HS_CLK_N

6.0

(152.4)

See (3)

(mm)

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

6.0

(152.4)

See (3)

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_LS_CLK

6.5

(165.1)

See (3)

(mm)

DMD_LS_WDATA

6.5

(165.1)

See (3)

(mm)

DMD_LS_RDATA

6.5

(165.1)

See (3)

(mm)

DMD_DEN_ARSTZ

7.0

(177.8)

See (3)

(mm)

(1)

Maximum signal routing length includes escape routing.

(2)

Multi-board DMD routing length is more restricted due to the impact of the connector.

(3)

Due to PCB variations, these recommendations cannot be defined. Any board design should SPICE simulate with the controller IBIS

model (found under the Tools & Software tab of the controller web page) to ensure routing lengths do not violate signal requirements.

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