DLPA2000 datasheet(38/63 Pages) TI

38 / 63 page

DMD_LS_RDATA

DMD_LS_CLK

DMD_HS_WDATA_B_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_C_P

600-MHz sub-LVDS DDR (High Speed)

DMD_HS_WDATA_D_N

DMD_HS_WDATA_D_P

DMD_HS_CLK_N

DMD_HS_CLK_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_H_P

DMD_HS_WDATA_A_N

DMD_HS_WDATA_A_P

(Example DMD)

DLP230xx

960 × 540 display

Sub-LVDS-DMD

120-MHz SDR (Low Speed)

DLPC34xx

Leave Open

DMD_LS_WDATA

DMD_DEN_ARSTZ

Figure 7-9. DLP160AP (0.16 QnHD) DMD Interface Example

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the

total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses,

and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires

attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control

and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both

waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity).

Variation from these recommendations may also work, but should be confirmed with PCB signal integrity

analysis or lab measurements.

DLPC3420

DLPS232 – OCTOBER 2021

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