SH7041A datasheet(518/923 Pages) RENESAS

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• Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains received data.

Bit 6: RDRF

Description

RDR does not contain valid received data (initial value)

RDRF is cleared to 0 when the chip is power-on reset or enters standby mode,

software reads RDRF after it has been set to 1, then writes 0 in RDRF, or the

DMAC or DTC reads data from RDR

RDR contains valid received data

RDRF is set to 1 when serial data is received normally and transferred from RSR

to RDR

Note:

The RDR and RDRF are not affected by detection of receive errors or by clearing of the RE

bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set

to 1 when reception of the next data ends, an overrun error (ORER) occurs and the

received data is lost.

• Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an

overrun error.

Bit 5: ORER

Description

Receiving is in progress or has ended normally (initial value). Clearing the RE bit

to 0 in the serial control register does not affect the ORER bit, which retains its

previous value.

ORER is cleared to 0 when the chip is power-on reset or enters standby mode or

software reads ORER after it has been set to 1, then writes 0 in ORER

A receive overrun error occurred. RDR continues to hold the data received

before the overrun error, so subsequent receive data is lost. Serial receiving

cannot continue while ORER is set to 1. In the clock synchronous mode, serial

transmitting is disabled.

ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1

SH7041A bảng dữ liệu(PDF) 518 Page - Renesas Technology Corp