SH7041A datasheet(519/923 Pages) RENESAS

519 / 923 page

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• Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing

error in the asynchronous mode.

Bit 4: FER

Description

Receiving is in progress or has ended normally (initial value). Clearing the RE bit

to 0 in the serial control register does not affect the FER bit, which retains its

previous value.

FER is cleared to 0 when the chip is power-on reset or enters standby mode or

software reads FER after it has been set to 1, then writes 0 in FER

A receive framing error occurred. When the stop bit length is two bits, only the

first bit is checked to see if it is a 1. The second stop bit is not checked. When a

framing error occurs, the SCI transfers the receive data into the RDR but does

not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock

synchronous mode, serial transmitting is also disabled.

FER is set to 1 if the stop bit at the end of receive data is checked and found to

be 0

• Bit 3—Parity Error (PER): Indicates that data reception (with parity) ended abnormally due to

a parity error in the asynchronous mode.

Bit 3: PER

Description

Receiving is in progress or has ended normally (initial value). Clearing the RE bit

to 0 in the serial control register does not affect the PER bit, which retains its

previous value.

PER is cleared to 0 when the chip is power-on reset or enters standby mode or

software reads PER after it has been set to 1, then writes 0 in PER

A receive parity error occurred. When a parity error occurs, the SCI transfers the

receive data into the RDR but does not set RDRF. Serial receiving cannot

continue while PER is set to 1. In the clock synchronous mode, serial transmitting

is also disabled.

PER is set to 1 if the number of 1s in receive data, including the parity bit, does

not match the even or odd parity setting of the parity mode bit (O/

E) in the serial

mode register (SMR)

SH7041A bảng dữ liệu(PDF) 519 Page - Renesas Technology Corp