SH7041A datasheet(514/923 Pages) RENESAS

514 / 923 page

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14.2.6

Serial Control Register (SCR)

The serial control register (SCR) operates the SCI transmitter/receiver, selects the serial clock

output in the asynchronous mode, enables/disables interrupt requests, and selects the

transmit/receive clock source. The CPU can always read and write the SCR. The SCR is initialized

to H'00 by a power-on reset or in standby mode. Manual reset does not initialize SCR.

Bit:

TIE

RIE

MPIE

TEIE

CKE1

CKE0

Initial value:

R/W:

R/W

• Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt

(TxI) requested when the transmit data register empty bit (TDRE) in the serial status register

(SSR) is set to 1 by transfer of serial transmit data from the TDR to the TSR.

Bit 7: TIE

Description

Transmit-data-empty interrupt request (TxI) is disabled (initial value).

The TxI interrupt request can be cleared by reading TDRE after it has

been set to 1, then clearing TDRE to 0, or by clearing TIE to 0.

Transmit-data-empty interrupt request (TxI) is enabled

• Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RxI)

requested when the receive data register full bit (RDRF) in the serial status register (SSR) is set

to 1 by transfer of serial receive data from the RSR to the RDR. It also enables or disables

receive-error interrupt (ERI) requests.

Bit 6: RIE

Description

Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)

requests are disabled (initial value). RxI and ERI interrupt requests can

be cleared by reading the RDRF flag or error flag (FER, PER, or ORER)

after it has been set to 1, then clearing the flag to 0, or by clearing RIE

to 0.

Receive-data-full interrupt (RxI) and receive-error interrupt (ERI)

requests are enabled.

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