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SH7041A bảng dữ liệu(PDF) 511 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
PDF  923 Pages
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7041A bảng dữ liệu(HTML) 511 Page - Renesas Technology Corp

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The CPU cannot read or write the TSR directly.
Bit:
7
6
5
4
3
2
1
0
R/W:
—
—
—
—
—
—
—
—
14.2.4
Transmit Data Register (TDR)
The transmit data register (TDR) is an 8-bit register that stores data for serial transmission. When
the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written in the
TDR into the TSR and starts serial transmission. Continuous serial transmission is possible by
writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a power-on reset
or in standby mode. Manual reset does not initialize TDR.
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14.2.5
Serial Mode Register (SMR)
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset
or in standby mode. Manual reset does not initialize SMR.
Bit:
7
6
5
4
3
2
1
0
C/
A
CHR
PE
O/
E
STOP
MP
CKS1
CKS0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W



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