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SH7041A bảng dữ liệu(PDF) 356 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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nhà sản xuất  RENESAS [Renesas Technology Corp]
Trang chủ  http://www.renesas.com
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SH7041A bảng dữ liệu(HTML) 356 Page - Renesas Technology Corp

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Figure 12.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1,
OLSP = 1.
TCNT3 and
TCNT4 values
TGR3A
TGR4A
H'0000
Positive
phase output
Reverse
phase output
TDDR
TCNT4
TCNT3
Time
Active
level
Initial
output
Initial
output
Compare match
output (up count)
Compare match
output (up count)
Compare match
output (down count)
Compare match
output (down count)
Active level
Active level
Figure 12.2 Complementary PWM Mode Output Level Example
12.2.12
Timer Gate Control Register (TGCR)
The timer gate control register (TGCR) is an 8-bit read/write register that controls the waveform
output necessary for brushless DC motor control in complementary PWM mode/reset-
synchronized PWM mode. The TGCR is initialized to H'80 by a power-on reset or in the standby
mode. Manual reset does not initialize TGCR. These register settings are ineffective for anything
other than complementary PWM mode/reset-synchronized PWM mode.
Bit:
7
6
5
4
3
2
1
0
—
BDC
N
P
FB
WF
VF
UF
Initial value:
1
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
• Bit 7—Reserved: This bit always reads as 1. The write value should always be 1.



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