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SH7041A bảng dữ liệu(PDF) 355 Page - Renesas Technology Corp

tên linh kiện SH7041A
Giải thích chi tiết về linh kiện  Renesas 32-Bit Single-Chip RISC Microprocessor SuperH RISC engine Family/SH7040 Series(CPU Core SH-2)
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12.2.11
Timer Output Control Register (TOCR)
The timer output control register (TOCR) enables/disables PWM synchronized toggle output in
complementary PWM mode and reset sync PWM mode, and controls output level inversion of
PWM output. The TOCR is initialized to H'00 by a power-on reset or in the standby mode.
Manual reset does not initialize TOCR. These register settings are ineffective for anything other
than complementary PWM mode/reset-synchronized PWM mode.
Bit:
7
6
5
4
3
2
1
0
—
PSYE
—
—
—
—
OLSN
OLSP
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R
R
R
R
R/W
R/W
• Bits 7, 5–2—Reserved: These bits always read as 1. The write value should always be 1.
• Bit 6—PWM Synchronous Output Enable (PSYE): Selects the enable/disable of toggle output
synchronized with the PWM period.
Bit 6: PSYE
Description
0
Toggle output synchronous with PWM period disabled (initial value)
1
Toggle output synchronous with PWM period enabled
• Bit 1—Output Level Select N (OLSN): Selects the reverse phase output level of the
complementary PWM mode or reset-synchronized PWM mode.
Compare Match Output
OLSN
Initial Output
Active Level
Increment Count
Decrement Count
0
High level*
Low level
High level
Low level (initial
value)
1
Low level*
High level
Low level
High level
Note: * The reverse phase waveform initial output value changes to active level after elapse of the
dead time after count start.
• Bit 0—Output Level Select P (OLSP): Selects the positive phase output level of the
complementary PWM mode or reset-synchronized PWM mode.
Compare Match Output
OLSP
Initial Output
Active Level
Increment Count
Decrement Count
0
High level
Low level
Low level
High level (initial value)
1
Low level
High level
High level
Low level



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