STE2007DIE2 datasheet(20/62 Pages) STMICROELECTRONICS

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4 INTERFACE

STE2007

20/62

Figure 10. 4-lines SPI Commands Transfe

Figure 11. 4-lines SPI Video Data Write Cycle

4.2.1.1 Data/Command Transfer break

If the Host processor generates an break condition (!CS Line HIGH before having received Bit

D0) while transferring a Data byte to the Frame Memory or a Command identifier or a command

parameter, the not complete received byte is discarded, the communication is interrupted and

the interface is forced in reset state.

When !CS line becomes low again to start a new communication session STE2007 is ready to

receive the same byte interrupted re-transmitted or a new command identifier.

Figure 12. 4-lines SPI Data Transfer break condition

4.2.1.2 Data/Command Transfer pause

It is possible while transferring Frame Memory Data, Commands or Command Parameters to

insert a pause in the data transmission (!CS Line HIGH after 8 Bits Received). When !CS is

forced high after a whole byte received, the received byte is processed. Then STE2007 is

forced in a wait state ready to restart processing incoming data from the point where the

communication has been paused

LR0189

Hi-Z

COMMAND

D/!C

!CS

SDA

(input)

SCL

SDA

(output)

LR0190

Hi-Z

COMMAND

DATA to VIDEO RAM

D/!C

!CS

SDA

(input)

SCL

SDA

(output)

DATA to VIDEO RAM

D/!C

!CS

SDA

SCL

LR0192

COMMAND/PARAMETER

Break

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