STE2007DIE2 datasheet(13/62 Pages) STMICROELECTRONICS

13 / 62 page

STE2007

3 Display Driver Electrical Characteristics

13/62

Table 11.

Input Signals Change Time

3.4.1

Driver TxData Mode

Table 12.

Timings based on 4 MHz SCLK Speed

Note: 1 Data Hold Time T1 depends on SCLK high time and Max Data Hold time. It is Always 3-8ns

before SCLK pulse falling edge

2 The input signal rise and fall times must be within 10ns.

3 Every timing is specified on the basis of 30% and 70% of VDDI.

4Tamb = -40 to 85°C, unless otherwise specified.

Table 13.

Timings based on 1 MHz SCLK Speed

Note: 1 The input signal rise and fall times must be within 10ns.

2 Every timing is specified on the basis of 30% and 70% of VDDI.

3Tamb = -40 to 85°C, unless otherwise specified.

Signal

Symbol

Parameter

Minimum

Typical/

Nominal

Maximum

Unit / Notes

Inputs

tr,tf

ns / to 30% & 70% levels

Item

Symbol

Condition

Rating

Units

Min.

Max.

Data hold time

Note 1

100

125

Access time

–

100

Output disable time

–

100

Data setup time

–

100

–

!CS pulse width high

–

250

Item

Symbol

Condition

Rating

Units

Min.

Max.

Data hold time *)

–

100

125

Access time

–

450

Output disable time

–

450

Data setup time

–

100

–

1CS pulse width high

–

250

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