STE2007 datasheet(40/62 Pages) STMICROELECTRONICS

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7 Power ON/Power OFF timing Sequence

STE2007

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Power ON/Power OFF timing Sequence

Figure 33 is the timing diagram for power on/power down sequences.

Figure 33. Timing for phone’s power on sequence when VDD,VDDCP Up before VDDI

XCS,SDAIN,XRES can become ”High” simultaneously with VDDI (tcs>0,tpi>0;tp2>0).

trs= max 5000ns (Internal Reset Time- see AC Characteristics Paragraph)

tPWROFF1>0ms must be considered when driver is in Power Saver or Booster OFF status

tPWROFF2>20ms must be considered when driver is in Normal Working Condition

VDDI, VDD and VDD_CP can come up/go down in any sequence

VDDI can be Up with VDD, VDDCP down and viceversa. If only one supply rail is up, the driver

is forced in reset state.

If VDD is high after VDDI all timing referred to VDDI must be referred to VDD (Fig. 24)

Figure 34. Timing for phone’s power on sequence when VDDI Up before VDD

VDDI

VDD

!RES

INTERNAL

RESET

tp2 >0

µs

tp1 > 0

trs = max. 5

µs

Reset State

!CS

Trs = max. 5

µs

tPWROFF1 >0 ms

tPWROFF2 >20ms

tp1 > 0

tcs >0

µs

Inputs

tpi >0

µs

tpi >0

µs

Outputs

High-Z

tcs >0

µs

VDDI

VDD

!RES

INTERNAL

RESET

tp2 >0

µs

tp1 < 0

trs = max. 5

µs

Reset State

!CS

Trs = max. 5

µs

tPWROFF1 >0 ms

tPWROFF2 >20ms

tp1 < 0

tcs >0

µs

SDAIN

tpi >0

µs

tpi >0

µs

SDAOUT

High-Z

tcs >0

µs

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