TUSB6250 datasheet(39/124 Pages) TI

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Interrupts

7−4

SLLS535A − January 2004

TUSB6250

7.2

Additional Interrupt Sources

All nonstandard 8051 interrupts (USB, I2C, ATA/ATAPI etc.) are OR-ed to generate an internal INT5. INT5 is

an active low-level interrupt (not edge triggered). A vector interrupt register is provided to identify all interrupt

sources (see section 7.2.1 VECINT: Vector Interrupt Register (ESFR at F7) for more details). Up to 64 interrupt

vectors are provided. It is the responsibility of the MCU to read the vector and dispatch the proper interrupt

routine.

The VECINT register is cleared by a power-up reset or a WDT reset. It can also be cleared by a USB reset,

when the function reset connection bit in the USBCTL register is set (FRSTE = 1). All the interrupts pending

in the queue are cleared once any of the above reset events occur.

7.2.1 VECINT: Vector Interrupt Register (ESFR at F7)

The VECINT register contains a vector value, which identifies the internal interrupt source that trapped to

location 0x202B hex. Writing any value to the VECINT register removes the vector and updates the next vector

value (if another interrupt is pending). Note that the vector value is offset, therefore, its value is in increments

of two (bit 0 is set to 0). When no interrupt is pending, the vector is set to 00h. As shown in Table 7−2, the

interrupt vector is divided into two fields: I[2:0] and G[3:0]. The I-field defines the interrupt source within a group

(on a first come, first serve basis) and the G-field defines the group number. Group G0 is the lowest and G15

is the highest priority.

765

43210

R/O

BIT

NAME

RESET

FUNCTION

3−1

I[2:0]

This field defines the interrupt source in a given group. See Table 7−2. Bit 0 is always = 0, therefore,

vector values are offset by two.

7−4

G[3:0]

This field defines the interrupt group. I[2:0] and G[3:0] combine to produce the actual interrupt vector.

Table 7−2. Vector Interrupt Values

G [3:0]

(HEX)

I [2:0]

(HEX)

VECTOR

(HEX)

INTERRUPT SOURCE

No interrupt

Input endpoint-1 ACK

Input endpoint-2 ACK

Input endpoint-3 ACK

Input endpoint-4 ACK

Input endpoint-1 NACK

Input endpoint-2 NACK

Input endpoint-3 NACK

Input endpoint-4 NACK

Output endpoint-1 ACK

Output endpoint-2 ACK

Output endpoint-3 ACK

Output endpoint-4 ACK

Output endpoint-1 NACK

Output endpoint-2 NACK

Output endpoint-3 NACK

Output endpoint-4 NACK

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