PIC16F684-ESLASHST datasheet(98/164 Pages) MICROCHIP

98 / 164 page

PIC16F684

DS41202C-page 96

Preliminary

 2004 Microchip Technology Inc.

12.3.4

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Detect. The Power-up Timer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 3.4 “Internal Clock Modes”. The chip is kept

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A config-

uration bit, PWRTE, can disable (if set) or enable (if

cleared or programmed) the Power-up Timer. The

Power-up Timer should be enabled when Brown-out

Detect is enabled, although it is not required.

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

•VDD variation

• Temperature variation

• Process variation

See

parameters

for

details

(Section 15.0

“Electrical Specifications”).

12.3.5

BROWN-OUT DETECT (BOD)

The BODEN0 and BODEN1 bits in the Configuration

Word register select one of four BOD modes. Two

modes have been added to allow software or hardware

control of the BOD enable. When BODEN<1:0> = 01,

the SBODEN bit (PCON<4>) enables/disables the

BOD allowing it to be controlled in software. By select-

ing BODEN<1:0>, the BOD is automatically disabled in

Sleep to conserve power and enabled on wake-up. In

this

mode,

the SBODEN

bit

disabled.

See

If VDD falls below VBOD for greater than parameter

(TBOD) (see Section 15.0 “Electrical Specifica-

tions”), the Brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not insured to occur if VDD falls below VBOD for less

than parameter (TBOD).

On any Reset (Power-on, Brown-out Detect, Watchdog

timer, etc.), the chip will remain in Reset until VDD rises

above VBOD (see Figure 12-3). The Power-up Timer

will now be invoked, if enabled and will keep the chip in

Reset an additional 64 ms.

If VDD drops below VBOD while the Power-up Timer is

running, the chip will go back into a Brown-out Detect

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOD, the Power-up Timer will execute a

64 ms Reset.

12.3.6

BOD CALIBRATION

The PIC16F684 stores the BOD calibration values in

fuses located in the Calibration Word register (2008h).

The Calibration Word register is not erased when using

the specified bulk erase sequence in the “PIC12F6XX/

16F6XX

Memory

Programming

Specification”

(DS41204) and thus, does not require reprogramming.

FIGURE 12-3:

BROWN-OUT SITUATIONS

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

Note:

Address 2008h is beyond the user program

memory space. It belongs to the special

configuration

memory

space

(2000h-

3FFFh), which can be accessed only during

programming. See “PIC12F6XX/16F6XX

Memory

Programming

Specification”

(DS41204) for more information.

64 ms(1)

VBOD

VDD

Internal

Reset

VBOD

VDD

Internal

Reset

64 ms(1)

< 64 ms

64 ms(1)

VBOD

VDD

Internal

Reset

Note 1:

64 ms delay only if PWRTE bit is programmed to ‘0’.

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