PIC16F684-ESLASHST datasheet(30/164 Pages) MICROCHIP

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PIC16F684

DS41202C-page 28

Preliminary

 2004 Microchip Technology Inc.

FIGURE 3-9:

FSCM TIMING DIAGRAM

3.7.2

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at

any point after the device has exited a Reset or Sleep

condition and the Oscillator Start-up Timer (OST) has

expired. If the external clock is EC or RC mode,

monitoring will begin immediately following these

events.

For LP, XT or HS mode, the external oscillator may

require a start-up time considerably longer than the

FSCM sample clock time, a false clock failure may be

detected (see Figure 3-9). To prevent this, the internal

oscillator is automatically configured as the system

clock and functions until the external clock is stable

(the OST has timed out). This is identical to

Two-Speed Start-up mode. Once the external oscilla-

tor is stable, the LFINTOSC returns to its role as the

FSCM source.

OSCFIF

CM Output

System

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit (OSCCON<3>) to verify the

oscillator

start-up

and

system

clock

switchover has successfully completed.

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