AM79C978AVCW datasheet(38/256 Pages) AMD

38 / 256 page

Am79C978A

Figure 11.

Address Parity Error Response

During the data phase of an I/O write, memory-mapped

I/O write, or configuration write command that selects

the Am79C978A controller as target, the device sam-

ples the AD[31:0] and C/BE[3:0] lines for parity on the

clock edge, and data is transferred as indicated by the

assertion of IRDY and TRDY. PAR is sampled in the fol-

lowing clock cycle. If a parity error is detected and re-

porting of that error is enabled by setting PERREN

(PCI Command register, bit 6) to 1, PERR is asserted

one clock later. The parity error will always set PERR

(PCI Status register, bit 15) to 1 even when PERREN

is cleared to 0. The Am79C978A controller will finish a

transaction that has a data parity error in the normal

way by asserting TRDY. The corrupted data will be writ-

ten to the addressed location.

Figure 12 shows a transaction that suffered a parity

error at the time data was transferred (clock 7, IRDY

and TRDY are both asserted). PERR is driven high at

the beginning of the data phase and then drops low due

to the parity error on clock 9, two clock cycles after the

data was transferred. After PERR is driven low, the

Am79C978A controller drives PERR high for one clock

cycle, since PERR is a sustained tri-state signal.

Figure 12.

Slave Cycle Data Parity Error Response

FRAME

CLK

SERR

C/BE

DEVSEL

2345

PAR

ADDR

1st DATA

CMD

PAR

22399A-14

FRAME

CLK

IRDY

TRDY

C/BE

DEVSEL

PAR

ADDR

CMD

PAR

2345678

DATA

PAR

PERR

22399A-15

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