AT25SF321 datasheet(25/48 Pages) DIALOG

25 / 48 page

AT25SF321

DS-25SF321–047F–8/2017

9.2

Program Security Registers (42h)

The Program Security Registers command utilizes the internal 256-byte buffer for processing. Therefore, the contents of

the buffer will be altered from its previous state when this command is issued.

The Security Registers can be programmed in a similar fashion to the Program Array operation up to the maximum clock

frequency specified by fCLK. Before a Program Security Registers command can be started, the Write Enable command

must have been previously issued to the device (see “Write Enable (06h)” on page 20) to set the Write Enable Latch

(WEL) bit of the Status Register to a logical “1” state. To program the Security Registers, the CS pin must first be

asserted and the opcode of 42h must be clocked into the device. After the opcode has been clocked in, the three address

bytes must be clocked in to specify the starting address location of the first byte to program within the Security Register.

Table 9-2.

Security Register Addresses for Program Security Registers Command

Figure 9-2. Program Security Registers

9.3

Read Security Registers (48h)

The Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock

frequency specified by fCLK. To read the Security Register, the CS pin must first be asserted and the opcode of 48h must

be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify

the starting address location of the first byte to read within the Security Register. Following the three address bytes, one

dummy byte must be clocked into the device before data can be output.

After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in Security

device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping

around from the end of the register to the beginning of the register.

Address

A23-A16

A15-A8

A7-A0

Security Register 1

00H

01H

Byte Address

Security Register 2

00H

02H

Byte Address

Security Register 3

00H

03H

Byte Address

MSB

839

3738

3336

3132

2930

OPCODE

GH-

MPEDANCE

AAA

MSB

DDDDDDDD

ADDRESS BI

TS A23-

DATAI

NBYTE1

MSB

DDDDDDDD

DATAI

NBYTEn

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