AT25QL321 datasheet(16/79 Pages) DIALOG

16 / 79 page

AT25QL321

DS-25QL321–131C–5/2017

Notes:

Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being read from the device

on the IO pin.

SR = status register, The Status Register contents and Device ID will repeat continuously until CS terminates the instruction.

At least one byte of data input is required for Page Program, Quad Page Program and Program Security Register, up to 256 bytes



of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and



overwrite previously sent data.

See Manufacturer and Device Identification table for Device ID information.

Dual Input Address

IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0

IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1

Dual Output data

IO0 = (D6, D4, D2, D0)

IO1 = (D7, D5, D3, D1)

Quad Input Address

Set Burst with Wrap Input



IO0 = A20, A16, A12, A8, A4, A0, M4, M0

IO0 = x, x, x, x, x, x, W4,

IO1 = A21, A17, A13, A9, A5, A1, M5, M1

IO1 = x, x, x, x, x, x, W5, x

IO2 = A22, A18, A14, A10, A6, A2, M6, M2

IO2 = x, x, x, x, x, x, W6, x

IO3 = A23, A19, A15, A11, A7, A3, M7, M3

IO3 = x, x, x, x, x, x, x



Quad Input/ Output Data



IO0 = (D4, D0…)

IO1 = (D5, D1…)

IO2 = (D6, D2…)

IO3 = (D7, D3…)

Fast Read Quad I/O Data Output



IO0 = (x, x, x, x, D4, D0…)



IO1 = (x, x, x, x, D5, D1…)



IO2 = (x, x, x, x, D6, D2…)



IO3 = (x, x, x, x, D7, D3…)

10.

SC = security register

7.2

Write Enable (06h)

Write Enable instruction is for setting the Write Enable Latch (WEL) bit in the Status Register. The WEL bit must be set prior to

every Program, Erase and Write Status Register instruction. To enter the Write Enable instruction, CS goes low prior to the

instruction “06h” into Data Input (SI) pin on the rising edge of SCK, and then driving CS high.

Read Security Register

2Bh

(SC7-

SC0) (10)

Write Security Register

2Fh

Fast Read

Quad I/O

>80MHz

EBh

A23‐A16

A15‐A8

A7-A0

(M7-M0)

dummy

(D7‐D0)

>104MHz

A23‐A16

A15‐A8

A7-A0

(M7‐

M0)

dummy

(D7-

D0)

Reset Enable

66h

Reset

99h

Disable QPI

FFh

Burst

Read with

Wrap

>80MHz

0Ch

A23‐A16

A15‐A8

A7-A0

dummy

(D7‐D0)

>104MHz

A23‐A16

A15‐A8

A7-A0

dummy

(D7‐

D0)

Set Read Parameter

C0h

P7-P0

Quad Page Program

33h

A23‐A16

A15‐A8

A7-A0

(D7‐D0)

Table 7-5.

Instruction Set Table 4 (QPI instruction)

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