AT25QL321 datasheet(68/79 Pages) DIALOG

68 / 79 page

AT25QL321

DS-25QL321–131C–5/2017

Notes:

1. Clock high + Clock low must be less than or equal to 1/fc.

2. Value guaranteed by design and/or characterization, not 100% tested in production.

3. Contains: Read Status Register-1,2/ Read Manufacturer/Device ID, Dual, Quad/ Read JEDEC ID/ Read Security Register/ Read Serial

Flash Discovery Parameter.

4. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.

5. Commercial temperature only applies to Fast Read (FR). Industrial temperature applies to all other parameters.

Output Hold Time

tCLQX

tHO

1.5

HOLD Active Setup Time relative to Clock

tHLCH

HOLD Active Hold Time relative to Clock

tCHHH

HOLD Not Active Setup Time relative to Clock

tHHCH

HOLD Not Active Hold Time relative to Clock

tCHHL

HOLD to Output Low-Z

tHHQX(2)

tLZ

HOLD to Output High-Z

tHLQZ(2)

tHZ

Write Protect Setup Time Before CS Low

tWHSL(4)

Write Protect Setup Time After CS High

tSHWL(4)

100

CS High to Power Down Mode

tDP(2)

µs

CS High to Standby Mode without Electronic

Signature Read

tRES1(2)

µs

CS High to Standby Mode with Electronic

Signature Read

tRES2(2)

1.8

µs

CS High to next Instruction after Suspend

tSUS(2)

µs

CS High to next Instruction after Reset

tRST(2)

µs

Write Status Register Time

Byte Program Time

tBP

150

µs

Page Program Time

tPP

0.6

Page Program Time (ACC = 9V)

tEP

0.3

Block Erase Time(4KB)

tSE

0.06

0.4

Block Erase Time(32KB)

tBE1

0.20

1.5

Block Erase Time(64KB)

tBE2

0.35

Chip Erase Time

tCE

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