MPF7100BVMA2ES datasheet(46/125 Pages) NXP

46 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

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Product data sheet

Rev. 4 — 9 March 2021

46 / 125

• FAULT_CNT = FAULT_MAX_CNT

• Thermal shutdown tJ > TSD

• VIN_OVLO event when VIN_OVLO_SDWN = 1

Table 32. EWARN time configuration

OTP_EWARN_TIME[1:0]

EWARN delay time

100 μs

5 ms

20 ms

50 ms

When the EWARN pin is asserted, an interrupt is generated and the EWARN_I bit is set

to announce to the system of an imminent shutdown event.

In the OFF modes, EWARN remains de-asserted (pulled low).

In the event of a power loss (VIN removed), the EWARN pin is asserted upon crossing

the VWARNTH threshold to notify to the processor that VIN may be lost and allow some

time to prepare for the power loss.

Table 33. Early warning threshold

Symbol

Parameter

Min

Typ

Max

Unit

VWARNTH

Early warning threshold

2.7

2.8

2.9

14.9.8 PGOOD

PGOOD is an open-drain output programmable as a Power Good indicator pin or GPO.

In the application, PGOOD can be pulled up to VDDIO with a 100 kΩ resistor.

When OTP_PG_ACTIVE = 0, the PGOOD pin is used as a general-purpose output.

As a GPO, during the run state, the state of the pin is controlled by the RUN_PG_GPO

bit in the functional I2C registers:

• When RUN_PG_GPO = 1, the PGOOD pin is high

• When RUN_PG_GPO = 0, the PGOOD pin is low

During the standby state, the state of the pin is controlled by the STBY_PG_GPO bit in

the functional I2C registers:

• When STBY_PG_GPO = 1, the PGOOD pin is high

• When STBY_PG_GPO = 0, the PGOOD pin is low

When used as a GPO, the PGOOD pin can be enabled high as part of the

power up sequence as programmed by the OTP_SEQ_TBASE[1:0] and the

OTP_PGOOD_SEQ[7:0] bits. If enabled as part of the power up sequence, both the

RUN_PG_GPO and STBY_PG_GPO bits are loaded with 1, otherwise they are loaded

with 0 upon power up.

When OTP_PG_ACTIVE = 1, the PGOOD pin is in Power good (PG) mode and it acts as

a PGOOD indicator for the selected output voltages in the PF7100.

There is an individual PG monitor for every regulator. Each monitor provides an internal

PG signal that can be selected to control the status of the PGOOD pin upon an OV or UV

condition when the corresponding SWxPG_EN / LDOxPG_EN bits are set. The status

of the PGOOD pin is a logic AND function of the internal PG signals of the selected

monitors.

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