MPF7100BVBA2ES datasheet(105/125 Pages) NXP

105 / 125 page

NXP Semiconductors

PF7100

7-channel power management integrated circuit for high performance applications

PF7100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 9 March 2021

105 / 125

• I2C communication uses standard communication with no CRC and secure write

disabled.

• Default I2C address is 0x08 regardless of the address configured by OTP.

• Watchdog monitoring is disabled (including WDI and internal watchdog timer).

• The PF7100 can communicate through I2C as long as VDDIO is provided to the PMIC

externally.

The PAGE[2:0] bits are provided to grant access to the mirror registers and other OTP

dedicated bits. When device is in the TBB mode, it can access the mirror registers in

the extended register Page 1. With the TBBEN pin pulled low, access to the extended

The mirror registers are preloaded with the values form the OTP configuration. These

may be modified to set the proper power up configuration during TBB operation.

If a power up event is present with the TBBEN pin set high, device powers up with the

proper configuration but limited functionality.

Limited functionality includes:

• Default I2C address = 0x08

• CRC and secure write disabled

• Watchdog operation/monitoring disable

In order to allow TBB operation with full functionality, the TBBEN pin must be low when

the power up event occurs.

The PF7100 can operate normally using the TBB configuration, as long as VIN does not

go below the UVDET threshold. If VIN is lost (VIN < UVDET), the mirror register is reset

and TBB configuration must be performed again.

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