M69KB096AA datasheet(33/48 Pages) STMICROELECTRONICS

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M69KB096AA

Table 16. Synchronous Burst Read AC Characteristics

Note: 1. All the tests are performed with the outputs configured in “Full drive” strength (BCR5=’0’).

2. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The High-Z timings measure a

transition of 100mV between VOH or VOL and VCCQ/2.

3. These timings have been obtained with the AC Measurement Load Circuit shown on Figure 14.. The transition timings measure a

transition of 100mV between the High-Z level (VCCQ/2) and VOH or VOL.

4. Clock rates lower than 50MHz (clock period higher than 20ns) are allowed as long as tELKH specifications are met.

5. When configured in Synchronous mode (BCR15 = 0), a refresh opportunity must be provided every tELEH. A refresh opportunity is

satisfied by either of the following two conditions: E = VIH during Clock input K rising edge or E = VIH for longer than 15ns.

Symbol

Alt.

Parameter

M69KB096AA

Unit

80MHz

66MHz

Min

Max

Min

Max

tKHQV1

tABA

Burst Access Time

46.5

tKHQV2

tACLK

Delay From Clock High to Output Valid

tAVLH

tAVS

Address Valid to L High

tGLQV

tBOE

Delay From Output Enable Low to Output Valid in Burst mode

tEHEL

(5)

tCBPH

Chip Enable High between Subsequent Mixed-Mode Read

Operations

tELTV

tCEW

Chip Enable Low to WAIT Valid

7.5

tELEH

(5)

tCEM

Maximum Chip Enable Low Pulse

tKHKH

(4)

tCLK

Clock Period

12.5

tELKH

tCSP

Chip Enable Low to Clock High

4.5

tKHAX

tKHBX

tKHWX

tKHEH

tKHLH

tHD

Hold Time From Active Clock Edge

tEHQZ

(2)

tHZ

Chip Enable High to Output Hi-Z

tKHKL

Clock Rise Time

Clock Fall Time

1.8

2.0

tKHTV

tKHTX

tKHTL

Clock High to WAIT Valid

Clock High to WAIT Transition

911

tKHQZ

tKHZ

Clock High to Output Hi-Z

tKHQX1

tKLZ

Clock High to Output Transition

tKHQX2

tKOH

Output Hold from Clock High

tKHKL

tKLKH

tKP

Clock High to Clock Low

Clock Low to Clock High

tGHQZ

(2)

tOHZ

Output Enable High to Output Hi-Z

tGLQX

(3)

tOLZ

Output Enable Low to Output Transition

tAVKH

tLLKH

tBLKH

tWHKH

tCHKH

tSP

Set-up Time to Active Clock Edge

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