M69KB096AA datasheet(19/48 Pages) STMICROELECTRONICS

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M69KB096AA

Refresh Configuration Register

The Refresh Configuration Register (RCR) is used

for two purposes:

■

to define how the self refresh of the PSRAM

array is performed

■

to enable Page Read operations.

Altering the self refresh parameters can dramati-

cally reduce current consumption in Standby

mode.

At power-up, RCR is initialized to 0070h.

Refer to Table 9. for the description of the Refresh

Configuration Register Bits.

Page Mode Operation Bit (RCR7). The

Page

Mode operation bit determines whether the Asyn-

chronous Page Read mode is enabled. At power-

up, the RCR7 bit is set to ‘0’, and so the Asynchro-

nous Page Read mode is disabled.

Temperature

Compensated

Refresh

Bits

(RCR6-RCR5). The Temperature Compensated

Refresh bits allow an adequate refresh rate to be

selected at one of four different temperature

thresholds: +15°C, +45°C, +70°C, and +85°C. The

default setting is +85°C. See the Temperature

Compensated Refresh section for more details.

Deep Power-Down Bit (RCR4). The Deep Pow-

er-Down bit enables or disables all refresh-related

operations. The Deep Power-Down mode is en-

abled when the RCR4 bit is set to ‘0’, and remains

enabled until this bit is set to ‘1’. At power-up, the

Deep Power-Down mode is disabled.

See the Deep Power-Down section for more de-

tails.

Partial Array Refresh Bits (RCR2-RCR0). The

Partial Array Refresh bits allow refresh operations

to be restricted to a portion of the total PSRAM ar-

ray. The refresh options can be full array, one

eighth, one quarter, one half, or none of the array.

These memory areas can be located either at the

top or bottom of the memory array. By default, the

full memory array is refreshed (see Table

8., Address Patterns for Partial Array Refresh).

Table 8. Address Patterns for Partial Array Refresh

Note: RCR4 is set to ‘1’.

RCR2

RCR1

RCR0

Refreshed Area

Address Space

Size of

Refreshe

d Area

Density

Full Array (Default)

000000h-3FFFFFh

4 Mbitsx16 64 Mbits

Bottom Half of the Array

000000h-1FFFFFh

2 Mbitsx16 32 Mbits

Bottom First Quarter of the Array

000000h-0FFFFFh

1 Mbitsx16 16 Mbits

Bottom First Eighth of the Array

000000h-07FFFFh

512Kbitsx

8 Mbits

None of the Array

Top Half of the Array

200000h-3FFFFFh

2 Mbitsx16 32 Mbits

Top Quarter of the Array

300000h-3FFFFFh

1 Mbitsx16 16 Mbits

Top One-Eighth of the Array

380000h-3FFFFFh

512Kbitsx

8 Mbits

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