SC3200 datasheet(407/447 Pages) AMD

407 / 447 page

AMD Geode™ SC3200 Processor Data Book

407

Electrical Specifications

Revision 5.1

Table 9-27. IDE UltraDMA Data Burst Timing Parameters

Symbol

Parameter

Mode 0

Mode 1

Mode 2

Unit

Comments

Min

Max

Min

Max

Min

Max

t2CYC

Typical sustained average two cycle time

240

160

120

Two cycle time allowing for clock variations

(from rising edge to next rising edge or from

falling edge to next falling edge of STROBE)

235

156

117

tCYC

Cycle time allowing for asymmetry and clock

variations (from STROBE edge to STROBE

edge)

114

tDS

Data setup time (at recipient)

tDH

Data hold time (at recipient)

tDVS

Data valid setup time at sender (from data

bus being valid until STROBE edge)

tDVH

Data valid hold time at sender (from

STROBE edge until data may become

invalid)

666

tFS

First STROBE time (for device to first negate

IDE_IRDY[0:1] (DSTROBE[0:1]) from

IDE_IOW[0:1]# (STOP[0:1]) during a data in

burst)

230

200

170

tLI

Limited interlock time

150

Note 1

tMLI

Interlock time with minimum

Note 1

tUI

Unlimited interlock time

Note 1

tAZ

Maximum time allowed for output drivers to

release (from being asserted or negated)

tZAH

Minimum delay time required for output driv-

ers to assert or negate (from released state)

tZAD

000

tENV

Envelope time (from IDE_DACK[0:1]# to

IDE_IOW[0:1]# (STOP[0:1]) and

IDE_IOR[0:1]# (HDMARDY[0:1]#) during

data out burst initiation)

tSR

STROBE to DMARDY time (if DMARDY# is

negated before this long after STROBE

edge, the recipient receives no more than

one additional data WORD)

tRFS

Ready-to-final-STROBE time (no STROBE

edges are sent this long after negation of

DMARDY#)

tRP

Ready-to-pause time (time that recipient

waits to initiate pause after negating

DMARDY#)

160

125

100

tIORDYZ

Pull-up time before allowing IDE_IORDY[0:1]

to be released

tZIORDY

Minimum time device waits before driving

IDE_IORDY[0:1]

000

tACK

Setup and hold times for IDE_DACK[0:1]#

(before assertion or negation)

tSS

Time from STROBE edge to negation of

IDE_DREQ[0:1] or assertion of

IDE_IOW[0:1]# (STOP[0:1]) (when sender

terminates a burst)

Note 1.

tUI, tMLI, and tLI indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipient) is wait-

ing for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock with no maximum time value. tMLI

is a limited timeout with a defined minimum. tLI is a limited time-out with a defined maximum.

SC3200 bảng dữ liệu(PDF) 407 Page - Advanced Micro Devices

SC3200 bảng dữ liệu(HTML) 407 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL