ACE25QC160GLDPTH datasheet(46/73 Pages) ACE

tên linh kiện	ACE25QC160GLDPTH

Giải thích chi tiết về linh kiện	16M BIT SPI NOR FLASH

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ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Read Security Registers (48H)

See Figure 27, the Read Security Registers instruction is similar to Fast Read instruction. The instruction is

followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge

of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being shifted out, at a

Max frequency fC, during the falling edge of SCLK. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out. Once

the A7-A0 address reaches the last byte of the register (Byte FFH), it will reset to 000H, the instruction is

completed by driving /CS high.

Address

A23-A16

A15-A12

A11-A8

A7-A0

Security Registers 1

00H

0001

0000

Byte Address

Security Registers 2

00H

0010

0000

Byte Address

Security Registers 3

00H

0011

0000

Byte Address

Figure27. Read Security Registers instruction Sequence Diagram (SPI Mode only)

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