HMC8193LC4TR-R5 datasheet(34/36 Pages) AD

34 / 36 page

HMC8193

Data Sheet

Rev. B | Page 34 of 36

SOLDERING INFORMATION AND RECOMMENDED

LAND PATTERN

Figure 119 and Figure 120 show the recommended land pattern

and solder stencil for the HMC8193, respectively. The HMC8193

is contained in a 4 mm × 4 mm, 24-terminal, ceramic, LCC

package, which has an exposed ground pad (EP). This pad is

internally connected to the ground of the chip. To minimize

thermal impedance and ensure electrical performance, solder

the pad to the low impedance ground plane on the PCB. To

further reduce thermal impedance, it is recommended that the

ground planes on all layers under the pad be stitched together

with vias.

The land pattern on the HMC8193 evaluation board provides a

simulated thermal resistance (θJA) of 120°C/W

.010" REF

.030"

MASK OPENING

.098" SQUARE MASK OPENING

.020 × 45" CHAMFER FOR PIN 1

.106" SQUARE

GROUND PAD

.116"

MASK

OPENING

PIN 1

.0197"

[0.50]

.034"

TYPICAL

VIA

SPACING

PAD SIZE

.026" × .010"

ᶲ .010"

TYPICAL VIA

GROUND PAD

SOLDERMASK

.004" MASK/METAL OVERLAP

.178" SQUARE

.010" MIN MASK WIDTH

Figure 119. Evaluation Board Land Pattern for the HMC8193 Package

0.020

TYP

0.008

TYP

0.019

TYP

0.024

TYP

0.094

0.176

SQUARE

0.017

0.094

R0.004

TYP

Figure 120. Solder Stencil for the HMC8193 Package on the HMC8193 Evaluation Board

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