MCP33131 datasheet(7/54 Pages) MICROCHIP

7 / 54 page

 2018 Microchip Technology Inc.

DS20006122A-page 7

MCP33131/MCP33121/MCP33111-XX

System Self-Calibration

Self-Calibration Time

tCAL

—500

650

(Note 2)

Number of SCLK Clocks for

Recalibrate Command

ReCalNSCLK

—

1024

—

clocks

Includes clocks for data bits

Serial Interface Timing Information: See Table 1-2

Digital Inputs/Outputs

High-level Input voltage

VIH

0.7 * DVIO

—DVIO + 0.3

DVIO ≥ 2.3V

0.9 * DVIO

—DVIO + 0.3

DVIO <2.3V

Low-level input voltage

VIL

-0.3

—

0.3 * DVIO

VDVIO ≥ 2.3V

-0.3

—

0.2 * DVIO

VDVIO <2.3V

Hysteresis of Schmitt Trigger Inputs

VHYST

—

0.2 * DVIO

—

All digital inputs

Low-level output voltage

VOL

——

0.2 * DVIO

VIOL =500 µA (sink)

High-level output voltage

VOH

0.8 * DVIO

—

IOL = - 500 µA (source)

Input leakage current

ILI

—

±1

µA

CNVST/SDI/SCLK = GND or DVIO

Output leakage current

ILO

—

±1

µA

Output is high-Z, SDO = GND or

DVIO

Internal capacitance

(all digital inputs and outputs)

CINT

—7

—

TA = 25°C (Note 1)

TABLE 1-1:

KEY ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF =5V,

GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN =10 kHz, CLOAD_SDO = 20 pF.

• MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.

• MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note

1: This parameter is ensured by design and not 100% tested.

2: This parameter is ensured by characterization and not 100% tested.

3: Decoupling capacitor is recommended on the following pins:

(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.

4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.

5: ENOB = (SINAD - 1.76)/6.02

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