TLE8082ES datasheet(47/61 Pages) INFINEON

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CSN

SCK

MSB

LSB

MSB

LSB

Request 1

Request 2

Request 3

Response 0

Response 1

Response 2

Figure 15

Send and response scheme

Definition of the response:

•

during power on reset: no SPI communication enabled - no response

•

1st response after power on reset: content of register Config (NOTE: consider power on reset time)

•

during operation reset: no SPI communication enabled - no response

•

1st response after operation reset: content of register Diag0 (NOTE: consider operation reset time)

•

1st response after NRIO reset: content of register Diag0 (NOTE: consider NRIO input filter time,

DIAG0.NRIORES set)

•

1st response after watchdog reset: content of register Diag0 (NOTE: DIAG0.WDRES is set)

•

response after correct communication: content of addressed register

•

response after invalid communication: content of register Diag0 (NOTE: DIAG0 content is not reliable)

RN/W bit of the response corresponds to the RN/W bit of the request for correct communication. For all other

responses the RN/W bit is "0" (read).

9.5

SPI timing diagram

High impedance

MSB

LSB

High impedance

CSN

SCK

undefined

CSN enable lead time

tCSN(lead)

SPI clock high time

tSCK(high)

SPI clock low time

tSCK(low)

SPI clock frequency

fSCK

SI data setup time

tSI(setup)

SI data hold time

tSI(hold)

SO data valid time

tSO(valid)

Sequential transfer delay time

tCSN(td)

CSN enable lag time

tCSN(lag)

SO enable time

tSO(enable)

SO disable time

tSO(disable)

Vin,h

Vin,l

Vin,h

Vin,l

Vin,h

Vin,l

Vout,h

Vout,l

SO rise and fall time

tSO(rise,fall)

undefined

Figure 16

Timing diagram

TLE8082ES

Small engine management IC

Serial Peripheral Interface (SPI)

Datasheet

Rev. 1.0

2021-03-23

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