TLE8082ES datasheet(46/61 Pages) INFINEON

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CSN

MSB

LSB

time

LSB

High Z

Shift

SO data

Sample

SI data

t [µs]

MSB

SCK

Figure 13

Communication frame

Note: This definition corresponds to AURIX™ microcontrollers to the mode definition clock polarity CPOL="0b" and

clock phase CPHA="1b".

9.3

SPI data frame

The data frame consist of 1 read/write bit (RN/W), 3 address bits (A2 to A0) and 12 data bits (D11 to D0)

according to the register definition.

Bit

RN/W

A0 D11 D10 D9

MSB

LSB

Address Bits

Read

Write

Bit

Data Bits

Figure 14

Data frame

A correct communication consists of 16 bits in one communication frame and the value of the address bits must

refer to an existing register.

All other communication frames are invalid.

9.4

SPI send and response scheme

The logical frame dependency is defined as out-of-frame communication where the logical response of the

slave is within the next frame of the master.

TLE8082ES

Small engine management IC

Serial Peripheral Interface (SPI)

Datasheet

Rev. 1.0

2021-03-23

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