MCP3462R-ESLASHST datasheet(82/118 Pages) MICROCHIP

82 / 118 page

MCP3461/2/4R

DS20006404C-page 82

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6.8.2

CONVERSION CYCLE START

INTERRUPT

This interrupt is the only selectable one and the only

one not present in the STATUS byte on the SDO and

IRQ registers. It is only available on the IRQ pin. The

user can enable or disable this output by using:

•[EN_STP] = 1: The conversion start interrupt

output is enabled (default).

•[EN_STP] = 0: The conversion start interrupt

output is disabled.

This interrupt marks the beginning of a conversion

cycle. In case of a One-Shot mode or Continuous mode

conversion in MUX mode, it marks the start of the

sampling in the first conversion (after the ADC start-up

delay of 256 DMCLK periods). In case of a Scan mode,

it marks the start of the sampling in the first conversion

of the first Scan mode cycle. The host MCU can utilize

this interrupt to synchronize the start of the ADC con-

version and manage synchronous events together with

the conversion process (see Figure 6-14 for more

details).

FIGURE 6-14:

Conversion Start IRQ Timing Diagram.

This interrupt output generates a falling edge on the

IRQ pin and is automatically cleared after a short

period of time, TSTP.

6.8.3

POR INTERRUPT

The POR interrupt informs the user if a POR event has

happened or if the part is in a POR state when the IRQ

pin is used.

This interrupt is implemented with three different and

independent mechanisms: STATUS byte on SDO, IRQ

6.8.3.1

STATUS Byte on SDO

When the device has just powered up, on the first

STATUS byte transmitted on SDO (first communica-

tion), the POR_STATUS bit is logic low. Once the

STATUS byte has been transmitted, the POR_STATUS

bit appears as ‘1’ until the part is powered down. If a

POR event occurs between two STATUS byte trans-

missions, and if the part is properly repowered up, the

POR_STATUS bit on SDO will appear as equal to ‘0’ on

the latter reading. This mechanism can only work when

the power supplies are back above the POR thresholds

on the analog and digital cores, as retrieving data from

the SPI port is not possible when the device is in a POR

state.

6.8.3.2

IRQ Register Status Bit

When the device has just powered up, the

POR_STATUS bit in the IRQ register is set to ‘0’. Once

the

IRQ

has

been

fully

read,

this

POR_STATUS bit is once again reset to ‘1’. If a POR

event occurs between two readings of the IRQ register,

the IRQ register Status bit will appear as equal to ‘0’ on

the second reading. This mechanism can only work

when the power supplies are back above the POR

thresholds on the analog and digital cores.

6.8.3.3

IRQ Pin State

A Logic Low state is generated on the IRQ pin as soon

as the AVDD or DVDD monitoring circuits detect a power

supply drop below their specified threshold.

This POR interrupt can only be cleared when both

AVDD and DVDD are above their monitoring voltage

thresholds. When this condition is met, the POR

threshold is cleared by the CS falling edge. Therefore,

it means that if a CS falling edge does not clear the IRQ

pin state, the POR event is still in effect.

ADC_MODE

IRQ

TADC_SETUP

TCON V

TSTP

Conversion

Start IRQ

(EN_STP = 1)

Data Ready

IRQ

Shutdown

ADC STATUS

1st Conv ers ion in

either MUX or SCAN mode

Sta rt-up

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