MCP3464 datasheet(55/108 Pages) MICROCHIP

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DS20006180D-page 55

MCP3461/2/4

5.14.3

SCAN MODE INTERNAL

RESOURCE CHANNELS

5.14.3.1

Analog Supply Voltage Reading

(AVDD)

During the conversion that reads AVDD in SCAN mode,

the multiplexer selection becomes 0x98 (AVDD-AGND),

which is equal to the analog power supply voltage.

Since AVDD is the highest voltage available in the chip,

when reading AVDD in SCAN mode, the gain of the

ADC is automatically set to 0.33x, which maximizes the

input full-scale range, regardless of the GAIN[2:0] set-

tings. This temporary internal configuration does not

change the register settings, but just for the gain of the

device during this conversion.

With this fixed 0.33x gain, the ADC can measure the

maximum specified analog supply voltage (AVDD =3.6V)

with a reference voltage as low as 1.2V.

5.14.3.2

Temperature Reading (TEMP)

During the conversion that reads TEMP in SCAN

mode, the multiplexer selection becomes 0xDE, which

enables the two temperature diode sensors at each

input of the ADC. During the temperature reading, the

gain of the ADC is automatically set to ‘1x’, regardless

of the GAIN[2:0] settings. This temporary internal con-

figuration does not change the register setting, but just

for the gain of the device during this conversion.

5.14.3.3

Offset Reading (OFFSET)

During the conversion that reads OFFSET in SCAN

mode, the differential MUX output is shorted to AGND

(internally). The Offset Reading varies from part to part,

over AVDD and temperature. The reading of this offset

value can be used for the device offset calibration or

tracking of the offset value in applications.

There is no automatic offset calibration in the device,

so the user has to manually write the opposite signed

value of the offset measured into the OFFSETCAL reg-

ister to effectively cancel the offset on the subsequent

outputs.

5.14.3.4

VCM Reading (VCM)

During the conversion that reads VCM, the device

monitors the internal Common-mode voltage of the

device in order to ensure proper operation.

The VCM voltage of the device should be located at 1.2V,

±2%, to ensure proper accuracy. In this setting, the inter-

nal multiplexer setting becomes 0xF8h (VCM – AGND). In

order to properly measure VCM, the voltage reference at

the inputs needs to be larger than 1.2V.

During the VCM reading, the gain of the ADC is set to

1x regardless of the GAIN[2:0] settings. This temporary

internal configuration does not change the register

setting, but just the gain of the device during this

conversion.

The VCM reading is susceptible to the gain error and off-

set error of the ADC, which should be calibrated out to

obtain a precise internal Common-mode measurement.

5.14.4

DELAY BETWEEN EACH

CONVERSION WITHIN A SCAN

CYCLE (DLY[2:0])

While the ADC and multiplexer are optimized to switch

from one channel to another instantaneously, it may not

be the case of an application that requires additional

settling time to overcome the transition. The device can

insert an additional delay between each conversion of

the SCAN cycle.

The delay value is controlled by the DLY[2:0] bits

located in the SCAN register (SCAN[23:20]). See

Table 5-15.

The delay is only added in between two conversions of

the same SCAN cycle. There is no delay added at the

end or the beginning of each SCAN cycle as a result of

the DLY[2:0] bits setting.

During this delay, the ADC is internally kept in Standby

mode (ADC_MODE[1:0] = 10 internally, but the

ADC_MODE[1:0] bits are always read as ‘11’ through

the SPI interface).

The analog multiplexer switches to the next selected

input at the end of each conversion, which means at

the beginning of the added delay so that the application

can have additional time to settle properly.

TABLE 5-15:

DELAY BETWEEN

CONVERSIONS WITH A SCAN

CYCLE

DLY[2:0]

Delay Value

(DMCLK Periods)

111

512

110

256

101

128

100

011

010

001

000

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