PIMXRT516SCVM5A datasheet(36/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Electrical characteristics

4.2.3.5

LPSR_LDO_ANA

LPSR_LDO_ANA provides 1.8 V power source (VDD_LPSR_ANA) from 3.3 V power domain

(VDD_LPSR_IN). Its default output value is 1.8 V. Two work modes are supported by this LDO: Low

Power mode and High Power mode. In Low Power mode, the LDO provides 2 mA (maximum value) by

consuming only 4 A current. In High Power mode, the LDO provides 75 mA current capacity with 40 A

static power dissipation.

4.2.4

DCDC

DCDC can be configured to operate on power-save mode when the load current is less than 50 mA. During

the power-save mode, the converter operates with reduced switching frequency in PFM mode and with a

minimum quiescent current to maintain high efficiency.

DCDC can detect the peak current in the P-channel switch. When the peak current exceeds the threshold,

DCDC will give an alert signal, and the threshold can be configured. By this way, DCDC can roughly

detect the current loading.

DCDC also includes the following protection functions:

•

Over current protection. In run mode, DCDC shuts down when detecting abnormal large current in

the P-type power switch.

•

Over voltage protection. DCDC shuts down when detecting the output voltage is too high.

•

Low voltage detection. DCDC shuts down when detecting the input voltage is too low.

Table 21 shows DCDC characteristics.

Table 19. LPSR_LDO_DIG specification

Specification

Min

Typ

Max

Unit

VDD_LPSR_ANA

1.71

1.8

1.89

VDD_LPSR_DIG

0.7

1.15

I_out

—

External decoupling capacitor

—

2.2

—

F

Table 20. LPSR_LDO_ANA specification

Specification

Min

Typ

Max

Unit

VDD_LPSR_IN

3.3

3.6

VDD_LPSR_ANA

—

1.8

—

I_out

—

External decoupling capacitor

—

4.7

—

F

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