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PIMXRT516SCVM5A bảng dữ liệu(PDF) 32 Page - NXP Semiconductors |
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PIMXRT516SCVM5A bảng dữ liệu(HTML) 32 Page - NXP Semiconductors |
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32 / 124 page  i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021 32 NXP Semiconductors Electrical characteristics 4.2 System power and clocks This section provides the information about the system power and clocks. 4.2.1 Power supplies requirements and restrictions The system design must comply with power-up sequence, power-down sequence, and steady state guidelines as described in this section to guarantee the reliable operation of the device. Any deviation from these sequences may result in the following situations: • Excessive current during power-up phase • Prevention of the device from booting • Irreversible damage to the processor (worst-case scenario) Figure 4 shows the power sequence. Table 14. Typical wakeup time1 1 Please refer to Table 13 for Set Point modes definition, and the only difference between Set Point #15 Standby Suspend mode and Set Point #15 Standby Stop mode is the Suspend mode versus Stop mode on CM4 core. Description Typical wakeup time Unit From Set Point #0 Standby Suspend to Set Point #0 normal drive RUN 4.13 ms From Set Point #5 Standby Suspend to Set Point #0 normal drive RUN 4.79 ms From Set Point #10 Standby Suspend to Set Point #0 normal drive RUN 5.47 ms From Set Point #15 Standby Stop to Set Point #0 normal drive RUN 7.6 ms From SNVS mode to ROM exit 8.54 ms |
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